1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a test circuit that facilitates testing of an integrated circuit mixedly including a large capacity memory circuit and a logic circuit, for example.
2. Description of the Related Art
Conventionally, in hybrid integrated circuits having multiple memory blocks mounted on the same chip, a structure (e.g., a cache memory) which shares the addresses of the individual memory blocks or a structure where a test circuit or the like shares the addresses of the individual memory blocks is often used. In this case, as described hereinafter, it is difficult to improve the precision of detecting defects originating from a memory block and to increase the testing efficiency, e.g., shortening the testing time, when a test is conducted to check the functions of a memory circuit.
The methods of testing memory circuits having the above structure are classified into two general categories. One is to use a tester or the like to supply the necessary signals to the memory circuit from outside the integrated circuit, and the other is a BIST (Built-In Self Testing) method which allows the device itself to produce the required test signals to conduct the test. In conducting such tests, the test efficiency will be improved if multiple memories are tested at a time using the shared addresses. However, the address spaces of different memory blocks often should not necessarily be the same.
FIG. 1 is a block diagram exemplifying an arrangement of a cache memory. A tag memory M1, a valid bit memory M2 and a data memory M3 having multiple lines have different address spaces. A column decoder 61 selects column address of the tag memory M1 using address signals A2 to A4. A column decoder 62 selects column address of the valid bit memory M2 using the address signals A2 to A4. A column decoder/line selector 63 selects a column address and a line for the data memory M3 using address signals A0 to A4. A row decoder 64 commonly selects row address of the individual memory blocks M1, M2 and M3 based on an address signal A5. A reference numeral 65 denotes a write/read circuit for the tag memory M1, 66 denotes a write/read circuit for the valid bit memory M2, and 67 denotes a write/read circuit for the data memory M3. A comparator/logic circuit 68 compares an tag address input with tag data which is read from the tag memory M1, checks valid bit data consisting of bits 1 to 4 and read from the valid bit memory M2, and outputs a control signal. A selector/buffer circuit 69 selectively outputs data which are read from multiple lines of the data memory M3, based on the control signal from the comparator/logic circuit 68.
The individual memory blocks M1, M2 and M3 share the address signals A2 to A5 of the address signals A0 to A5. However, the memory blocks M1 and M2 have narrower address space than the memory block M3 by the address signals A1 and A0. Therefore, when a test is conducted on the above cache memory based on the address of the data memory M3 having a large address space, the tag memory M1 and the valid bit memory M2 will access the same address multiple times while the entire addresses of the data memory M3 are circulated once. This will not be significant so much in a simple memory test, but will be significant when a memory test is performed with an improved high precision.
FIGS. 2A through 2C show examples of vectors of an N-system pattern (March) typically used in memory tests. A reference numeral 71 shows the size of a memory block, and 72 indicates the direction where the addresses are advanced. First, a value "0" is written in the entire memory cells from a smaller address to a larger one in FIG. 2A, then the value "0" is read from each memory cell, and then the value "1" is written in the same memory cell in FIG. 2B. In FIG. 2C, the value "1" is read from the memory cells from a larger address to a smaller one and the value "0" is then written in the same memory cell, as indicated by the vector directed opposite to the one in FIG. 2A.
FIGS. 3A and 3B are diagrams explaining the relationship between the address signals of a memory block and cell block selection when the cache memory in FIG. 1 is tested in accordance with the memory test vectors as shown in FIG. 2. FIG. 3A illustrates the relationship between the address signals of the tag memory M1 and valid bit memory M2, which have small address space, and the cell block selection. FIG. 3B illustrates the relationship between the address signals of the data memory M3 having a large address space, and the cell block selection. As shown in FIG. 3A-I, in the memory blocks M1 and M2 having small address spaces, the memory cell 1 is accessed when the address signals A2 and A3 are (0, 0). It is apparent from FIG. 3A-II that multiple accesses to the memory cell 1 are caused during when the address signals A2 and A3 are scanned sequentially from (0, 0) to (0, 1), (1, 0) and (1, 1) since the address signals A2 and A3 stay (0, 0) during such address scanning. On the other hand, each memory cell in the data memory M3 is accessed by the address signals A0, A1, A2 and A3, as shown in FIG. 3B-I. In accordance with the scanning of the address signals A0, A1, A2 and A3, the individual memory cells 1, 2, 3 and 4 are accessed sequentially, as shown in FIG. 3B-II. In other words, a memory having a small address space will access the same memory cells multiple times while an address not associated with the memory itself, i.e., an address of a memory having a large address space is being accessed. In this situation, since multiple writings will be caused in a single sequence on the same cell of the memory with the small memory space, the read output is likely to differ from the expected value.
with the use of a tester, this situation can be cleared by properly designing the test vectors. However, since test vectors for solid writing are normally used, this measure requires a huge number of vectors in proportion to the address space of a memory to be tested and thus, is not practical. For instance, if the tested memory is an 8K-byte memory, an N.sup.2 -system pattern for the memory needs 65 M bytes. It is therefore typical to employ a method of automatically generating an address by a tester. However, it is difficult to avoid the multiple accesses with this measure.
According to the BIST method, the memory itself automatically generates address signals and write data and compares the data to test the memory blocks. However, when it is necessary to test a memory with a more complex address pattern due to an increased capacity of memory blocks, the difference between the address spaces of multiple memory blocks would be critical. It would result in an increased testing time and an increased overhead of hardware, i.e., testing circuit.
Since a memory test for conventional semiconductor integrated circuits should be conducted for each of the multiple memory blocks with different address spaces mounted on the same chip, a longer testing time is required, otherwise, a large burden will be put on the test circuit or the generation of test vectors.